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(parent: 7262b9c) | patch
x86: Support more than 256 pins of ioapic.
authorKeir Fraser <keir.fraser@citrix.com>
Tue, 22 Sep 2009 13:18:51 +0000 (14:18 +0100)
committerKeir Fraser <keir.fraser@citrix.com>
Tue, 22 Sep 2009 13:18:51 +0000 (14:18 +0100)
commit34db292a4fe591bb7cdae25572c581577a0d9419
tree6d23171607a3478993fbae86ffc72423c412b761tree | snapshot
parent7262b9c0bcd2fa87bc69bc8f8b0645345dd0dc68commit | diff
x86: Support more than 256 pins of ioapic.

Some large system may have many ioapics which
have more than 256 pins totally. To support this
case, just let pirq == irq and build 1:1 mapping
between them, and this is based on the assumpation
that pirq == GSI number in dom0 for iopaic IRQs.

Thank Jan Beulich from Novell for reporting the issue
in pv_ops dom0.

Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
xen/arch/x86/io_apic.c diff | blob | history
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